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101 innovation drive san jose, ca 95134 www.altera.com cv-5v1-1.2 volume 1: device overview and datasheet cyclone v device handbook document last updated for alte ra complete design suite version: document publication date: 11.1 february 2012 cyclone v device handbook vo lume 1: device overview and datasheet
? 2012 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix word s and logos are trademarks of alte ra corporation and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specificat ions in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no respon sibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet iso 9001:2008 registered
february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v chapter 1. overview for cyclone v device family cyclone v features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 cyclone v family plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 low-power serial transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?8 pma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 pcs support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?9 pcie gen1 and gen2 hard ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?11 fpga gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?11 external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 adaptive logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 variable-precision dsp block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?13 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 dynamic and partial reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 clock networks and pll clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 enhanced configuration and configuration vi a protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 soc fpga with hps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 features of the hps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 system peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 hps?fpga axi bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 hps sdram controller subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 fpga configuration and processor booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 hardware and software development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?20 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?21 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?23 chapter 2. device datasheet for cyclone v devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 internal weak pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?13 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?20 memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?22 dqs logic block and memory output clock jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . 2?24 oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?24
iv contents cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?25 configuration specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 por specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 jtag configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 fpp configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 dclk-to-data[] ratio (r) for fpp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 fpp configuration timing when dclk to data[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?28 fpp configuration timing when dclk to data[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?30 as configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?32 ps configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?33 remote system upgrades circuitry timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?35 user watchdog internal oscillator frequency specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?35 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?35 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?36 programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?36 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?37 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?40 additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1
february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet chapter revision dates the chapters in this document, cyclone v device handbook, were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. overview for cyclone v device family revised: february 2012 part number: cv-51001-1.2 chapter 2. device datasheet for cyclone v devices revised: february 2012 part number: cv-51002-1.2
vi chapter revision dates cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet
cv-51001-1.2 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone v device handbook volume 1: device overview and datasheet february 2012 subscribe iso 9001:2008 registered 1. overview for cyclone v device family cyclone ? v devices are designed to simultaneously accommodate the shrinking power consumption, cost, an d time-to-market requirements; and the increasing bandwidth requirements for high-volum e and cost-sensitive applications. the cyclone v devices are ideal for small form factor applications that are cost- and power-sensitive in the wireless, wireline, military, broadcast, industrial, consumer, and communications industries. the cyclone v device family is available in six variants: cyclone v e?optimized for the lowest system cost and power requirement for a wide spectrum of general logic and digital signal processing (dsp) applications. cyclone v gx?optimized for the lowest cost and power requirement for 614-megabits per second (mbps) to 3.125- gigabits per second (gbps) transceiver applications. cyclone v gt?the fpga industry?s lowest cost and lowest power requirement for 5-gbps transceiver applications. cyclone v se?system-on-a-chip (soc) fpga with integrated cyclone v fpga and arm ? -based hard processor system (hps). cyclone v sx?soc fpga with integrat ed cyclone v fpga, arm-based hps, and 3.125-gbps transceivers. cyclone v st?soc fpga with integrat ed cyclone v fpga, arm-based hps, and 5-gbps transceivers. the cyclone v soc fpga variants feature an fpga integrated with an hps that consists of a dual-core arm cortex ? -a9 mpcore ? processor, a rich set of peripherals, and a shared multiport sdram controller. the cyclone v device family provides the following key advantages: up to 40% lower power consumption than the previous generation device?built on tsmc?s 28-nm low power (28lp) proce ss and includes an abundance of hard intellectual properties (ip). improved logic integration and differentiation capabilities?features a new 8-input adaptive logic modu le (alm), up to 11.6 megabits (mb) of dedicated memory, and variable-precision dsp blocks. increased bandwidth capacity?a combined result of the new 3-gbps and 5-gbps transceivers, and the ha rd memory controllers. tight integration of a dual-core arm cortex-a9 mpcore processor, hard ip, and an fpga in a single cyclone v soc fpga?supports over 100 gbps peak bandwidth with integrated data coherency between the processor and the fpga. february 2012 cv-51001-1.2
1?2 chapter 1: overview for cyclone v device family cyclone v features summary cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet cyclone v features summary some of the key features of the cyclone v devices include: built-in hard ip blocks support for all mainstream single-ended and differential i/o standards including 3.3 v at up to 16 ma drive strengths hps for the cyclone v se, sx, and st variants comprehensive design protection features to protect your valuable ip investments lowest system cost advantage?requires on ly two core voltages to operate, are available in low-cost wirebond packaging, and includes innovative cost saving features such as configuration via prot ocol (cvp) and partial reconfiguration table 1?1 lists a summary of the cyclone v features. table 1?1. summary of features for cyclone v devices (part 1 of 2) feature details technology tsmc?s 28-nm low power (28lp) process technology 1.1-v core voltage low-power high-speed serial interface 614 mbps to 5.0 gbps integrated transceiver speed transmitter pre-emphasis and receiver equalization dynamic partial reconfiguration of individual channels fpga general-purpose i/os (gpios) 875 mbps lvds receiver and 840 mbps lvds transmitter 400 mhz/800 mbps external memory interface on-chip termination (oct) 3.3-v support with up to 16 ma drive strength hard ip blocks embedded transceiver i/o pci express ? (pcie ? ) gen2 (x1 or x2) and gen1 (x1, x2, or x4) hard ip with multifunction support, endpoint, and root port variable-precision dsp native support for three signal processing precision levels (three 9 x 9s, two 18 x 19s, or one 27 x 27 multiplier) in the same variable-precision dsp block 64-bit accumulator and cascade embedded internal coefficient memory preadder/subtractor for improved efficiency memory controller ddr3, ddr2, lpddr, and lpddr2
chapter 1: overview for cyclone v device family 1?3 cyclone v features summary february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet hps (cyclone v se, sx, and st devices only) dual-core arm cortex-a9 mpcore processor?up to 800 mhz maximum frequency with support for symmetric and asymmetric multiprocessing interface peripherals?10/100/1000 ethernet media access control (mac), usb 2.0 on-the-go (otg) controller, serial peripheral interface (spi), quad spi flash controller, nand flash controller, sd/mmc/sdio controller, uart, controller area network (can), i2c interface, and up to 71 hps i/o interfaces system peripherals?general-purpose and watchdog timers, direct memory access (dma) controller, fpga configuration manager, and clock and reset managers on-chip ram and boot rom hps?fpga bridges?include the fpga-to-hps, hps-to-fpga, and lightweight hps-to-fpga bridges that allow the fpga fabric to master transactions to slaves in the hps, and vice versa. fpga-to-hps sdram controller subsystem?provid es a configurable interface to the multiport front end (mpfe) of the hps sdram controller arm coresight ? jtag debug access port, trace port, and on-chip trace storage high-performance fpga fabric enhanced 8-input alm with four registers internal memory blocks m10k?10-kilobits (kb) memory blocks with soft error correction code (ecc) memory logic array block (mlab)?640-bit distributed lutram where you can use up to 25% of the alms as mlab memory phase-locked loops (plls) precision clock synthesis, clock delay compensation, and zero delay buffering (zdb) integer mode and fractional mode clock networks 550 mhz global clock network global, quadrant, and peripheral clock networks clock networks that are not used can be powered down to reduce dynamic power configuration partial and dynamic reconfiguration of the fpga cvp active serial (as) x1 and x4, fast passive paralle l (fpp) x8 and x16, passive serial (ps), and jtag options enhanced advanced encryption standard (aes) design security features tamper protection packaging wirebond low-halogen packages multiple device densities with compatible package footprints for seamless migration between different device densities rohs-compliant options table 1?1. summary of features for cyclone v devices (part 2 of 2) feature details
1?4 chapter 1: overview for cyclone v device family cyclone v family plan cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet cyclone v family plan table 1?2 and table 1?3 list the cyclone v e, gx, an d gt maximum resource counts. table 1?2. maximum resource counts for cyclone v e devices? preliminary resource cyclone v e device 5cea2 5cea4 5cea5 5cea7 5cea9 alm 9,434 18,113 28,868 56,415 113,585 logic element (le) 25,000 48,000 76,500 149,500 301,000 block memory (kb) 1,700 2,700 3,800 6,500 11,600 mlab memory (kb) 196 270 440 836 1,717 variable-precision dsp block 25 72 124 156 342 18 x 19 multiplier 50 144 248 312 684 fractional pll 44666 gpio 288 288 272 480 448 lvds 100 100 100 122 122 hard memory controller11222 table 1?3. maximum resource counts for cyclone v gx and gt devices? preliminary resource cyclone v gx device cyclone v gt device 5cgxc3 5cgxc4 5cgxc5 5cgxc7 5cgxc9 5cgtd5 5cgtd7 5cgtd9 alm 11,698 18,868 28,868 56,415 113,585 28,868 56,415 113,585 le 31,000 50,000 76,500 149,500 301,000 76,500 149,500 301,000 block memory (kb) 1,400 2,500 3,800 6,500 11,600 3,800 6,500 11,600 mlab memory (kb) 147 295 440 836 1,717 440 836 1,717 variable-precision dsp block 42 70 124 156 342 124 156 342 18 x 19 multiplier 84 140 248 312 684 248 312 684 fractional pll (1) 46678678 3-gbps transceiver 3 6 6 9 12 ? ? ? 5-gbps transceiver ? ? ? ? ? 6 9 12 gpio 224 368 368 480 560 368 480 560 lvds 48 90 100 122 122 100 122 122 pcie hard ip block 12222222 hard memory controller 12222222 note to table 1?3 : (1) the maximum fractional plls listed includ e general purpose plls and transceiver plls.
chapter 1: overview for cyclone v device family 1?5 cyclone v family plan february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 1?4 and table 1?5 list the cyclone v se, sx, an d st maximum resource counts. table 1?4. maximum resource counts for cyclone v se devices? preliminary resource cyclone v se devices 5csea2 5csea4 5csea5 5csea6 alm 9,434 15,094 32,075 41,509 le 25,000 40,000 85,000 110,000 block memory (kb) 1,400 2,240 3,972 5,140 mlab memory (kb) 138 220 480 621 variable-precision dsp block 36 58 87 112 18 x 19 multiplier 72 116 174 224 fpga fractional pll 4 5 6 6 hps pll 3 3 3 3 fpga gpio 124 124 288 288 hps i/o 188 188 188 188 lvds 31 31 72 72 fpga memory controller ? 1 1 1 hps memory controller 1 1 1 1 arm cortex-a9 mpcore processor single- or dual-core single- or dual-core single- or dual-core single- or dual-core table 1?5. maximum resource counts for cyclone v sx and st devices? preliminary (part 1 of 2) resource cyclone v sx device cyclone v st device 5csxc4 5csxc5 5csxc6 5cstd5 5cstd6 alm 15,094 32,075 41,509 32,075 41,509 le 40,000 85,000 110,000 85,000 110,000 block memory (kb) 2,240 3,972 5,140 3,972 5,140 mlab memory (kb) 220 480 621 480 621 variable-precision dsp block 58 87 112 87 112 18 x 19 multiplier 116 174 224 174 224 fpga fractional pll (1) 56666 hps pll 3 3 3 3 3 3-gbps transceiver 6 9 9 ? ? 5-gbps transceiver ? ? ? 9 9 fpga gpio 124 288 288 288 288 hps i/o 188 188 188 188 188 lvds 31 72 72 72 72
1?6 chapter 1: overview for cyclone v device family cyclone v family plan cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 1?6 lists the cyclone v e, gx, and gt package plan that shows the gpio count, the maximum number of transceivers availabl e, and the vertical migration capability for each device package and density. pcie hard ip block 2 2 2 2 2 fpga memory controller 11111 hps memory controller 1 1 1 1 1 arm cortex-a9 mpcore processor dual-core dual-core dual-core dual-core dual-core note to table 1?5 : (1) the maximum fpga fractional plls listed include fpga general purpose plls and transceiver plls. table 1?5. maximum resource counts for cyclone v sx and st devices? preliminary (part 2 of 2) resource cyclone v sx device cyclone v st device 5csxc4 5csxc5 5csxc6 5cstd5 5cstd6 table 1?6. package plan for cyclone v e, gx, and gt devices? preliminary (1) device f256 (17 mm) u324 (15 mm) u484 (19 mm) f484 (23 mm) f672 (27 mm) f896 (31 mm) f1152 (35 mm) gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr gpio xcvr 5cea2 144 ? 176 ? 288 ? 288 ? ? ? ? ? ? ? 5cea4 144 ? 176 ? 288 ? 288 ? ? ? ? ? ? ? 5cea5 ? ? ? ? 272 ? 272 ? ? ? ? ? ? ? 5cea7 ? ? ? ? 240 ? 240 ? 336 ? 480 ? ? ? 5cea9 ? ? ? ? ? ? 224 ? 336 ? 448 ? ? ? 5cgxc3 (2) ? ? 112 3 208 3 208 3 ? ? ? ? ? ? 5cgxc4 (2) ? ? ? ? 224 6 240 6 336 6 ? ? ? ? 5cgxc5 (2) ? ? ? ? 224 6 240 6 336 6 ? ? ? ? 5cgxc7 (2) ? ? ? ? 240 6 240 6 336 9 480 9 ? ? 5cgxc9 (2) ? ? ? ? ? ? 224 6 336 9 448 12 560 12 5cgtd5 (3) ? ? ? ? 240 6 240 6 368 6 ? ? ? ? 5cgtd7 (3) ? ? ? ? 240 6 240 6 336 9 480 9 ? ? 5cgtd9 (3) ? ? ? ? ? ? 224 6 336 9 448 12 560 12 notes to table 1?6 : (1) the arrows indicate the packag e vertical migration capability. you can also migrate your desi gn across device densities in t he same packaging option if the devices have th e same dedicated pins, configur ation pins, and power pins. (2) the transceiver counts listed are for 3-gbps transceivers. (3) the transceiver counts listed are for 5-gbps transceivers.
chapter 1: overview for cyclone v device family 1?7 cyclone v family plan february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 1?7 lists the cyclone v se, sx, and st pack age plan that shows the fpga gpio and hps i/o counts, the maximum number of transceivers available, and the vertical migration capability for each device package and density. 1 to verify the pin migration compatibility, use the pin migration view window in the quartus ii software pin planner. f for more information about the verifying the pin migration compatibility, refer to the ?i/o management? chapter in the quartus ii handbook . table 1?7. package plan for cyclone v se, sx, and st devices? preliminary (1) device u484 (19 mm) u672 (23 mm) f896 (31 mm) gpio xcvr hps i/o gpio xcvr hps i/o gpio xcvr hps i/o 5csea2 66 ? 161 124 ? 188 ? ? ? 5csea4 66 ? 161 124 ? 188 ? ? ? 5csea5 66 ? 161 124 ? 188 288 ? 188 5csea6 66 ? 161 124 ? 188 288 ? 188 5csxc4 (2) ?? ? 1246 188 ?? ? 5csxc5 (2) ? ? ? 124 6 188 288 9 188 5csxc6 (2) ? ? ? 124 6 188 288 9 188 5cstd5 (3) ? ? ? ? ? ? 288 9 188 5cstd6 (3) ? ? ? ? ? ? 288 9 188 notes to table 1?7 : (1) the arrows indicate the packag e vertical migration capability. you can also migrate your desi gn across device densities in t he same packaging option if the devices have th e same dedicated pins, configur ation pins, and power pins. (2) the transceiver counts listed are for 3-gbps transceivers. (3) the transceiver counts listed are for 5-gbps transceivers.
1?8 chapter 1: overview for cyclone v device family low-power serial transceivers cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet low-power serial transceivers cyclone v devices deliver the industry?s lo west power 5-gbps transceivers at an estimated 88 mw maximum powe r consumption per channel. cyclone v transceivers are designed to be compliant for a wide range of protocols and data rates. the transceivers are positioned on the left outer edge of the device, as shown in figure 1?1 . the transceiver channels consist of the physical medium attachment (pma), physical coding sublay er (pcs), and clock networks. figure 1?1. device chip overview for cyclone v gx and gt devices (1) note to figure 1?1 : (1) this figure represents a cyclone v device wi th transceivers. other cyclone v devices ma y have a different floor plan than the one shown here. i/o, lvds, and memory interface i/o, lvds, and memory interface i/o, lvds, and memory interface transceiver pma blocks fractional plls hard pcs blocks fractional pll fractional plls pcie hard ip blocks hard memory controller hard memory controller core logic fabric and mlabs variable-precision dsp blocks m10k internal memory blocks distributed memory transceiver pma hard pcs transceiver pma hard pcs transceiver pma hard pcs clock networks transceiver individual channels
chapter 1: overview for cyclone v device family 1?9 low-power serial transceivers february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet pma support to prevent core and i/o noise from coupling into the transceivers, the pma block is isolated from the rest of the chip?ensuring optimal signal integrity. for the transceivers, you can use the channel pll of an unused receiver pma as an additional transmit pll. table 1?8 lists the pma features of the transceiver. pcs support the cyclone v core logic connects to the pcs th rough an 8-, 10-, 16-, 20-, 32-, or 40-bit interface, depending on the transceiver data rate and protocol. cyclone v devices contain pcs hard ip to support pcie gen1 and gen2, xaui, gbps ethernet (gbe), serial rapidio ? (srio), and common public radio interface (cpri). most of the other standard and proprietary protocols from 614 mbps to 5.0 gbps are supported. table 1?9 lists the pcs features of the transceiver. table 1?8. pma features of the transceivers in cyclone v devices features capability backplane support up to 16? fr4 pcb fabric drive capability at up to 5 gbps pll-based clock recovery superior jitter tolerance programmable deserialization and word alignment flexible deserialization width and configurable word alignment pattern equalization and pre-emphasis up to 6 db of pre-emphasis, up to 4 db of equalization, and no decision feedback equalizer (dfe) ring oscillator transmit plls 614 mbps to 5 gbps input reference clock range 20 mhz to 400 mhz transceiver dynamic reconfiguration allows the reconfiguration of a single channel without affecting the operation of other channels table 1?9. pcs features of the transceivers in cyclone v devices (part 1 of 2) pcs support data rates (gbps) transmitter datapath receiver datapath 3-gbps and 5-gbps basic 0.614 to 5.0 phase compensation fifo byte serializer 8b/10b encoder transmitter bit-slip word aligner deskew fifo rate-match fifo 8b/10b decoder byte deserializer byte ordering receiver phase compensation fifo pcie gen1: x1, x2, x4 pcie gen2: x1, x2 (1) 2.5 and 5.0 dedicated pcie phy ip core pipe 2.0 interface to the core logic dedicated pcie phy ip core pipe 2.0 interface to the core logic gbe 1.25 custom phy ip core with preset feature gbe transmitter synchronization state machine custom phy ip core with preset feature gbe receiver synchronization state machine
1?10 chapter 1: overview for cyclone v device family low-power serial transceivers cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet xaui 3.125 dedicated xaui phy ip core xaui synchronization state machine for bonding four channels dedicated xaui phy ip core xaui synchronization state machine for realigning four channels srio 1.3 and 2.1 1.25 to 3.125 custom phy ip core with preset feature srio version 2.1-compliant x2 and x4 channel bonding custom phy ip core with preset feature srio version 2.1-compliant x2 and x4 deskew state machine sdi, sd/hd, and 3g-sdi 0.27 (2) , 1.485, and 2.97 custom phy ip core with preset feature custom phy ip core with preset feature serial ata gen1 and gen2 1.5 and 3.0 custom phy ip core with preset feature electrical idle custom phy ip core with preset feature signal detect wider spread of asynchronous ssc cpri 4.1 (3) 0.6144 to 4.9152 dedicated deterministic latency phy ip core transmitter (tx) manual bit-slip mode dedicated deterministic latency phy ip core receiver (rx) deterministic latency state machine obsai rp3 0.768 to 3.072 dedicated deterministic latency phy ip core tx manual bit-slip mode dedicated deterministic latency phy ip core rx deterministic latency state machine v-by-one hs up to 3.75 custom phy ip core custom phy ip core wider spread of asynchronous ssc displayport 1.2 (4) 1.62 and 2.7 custom phy ip core custom phy ip core wider spread of asynchronous ssc higig 3.75 dedicated xaui phy ip core xaui synchronization state machine for bonding four channels dedicated xaui phy ip core xaui synchronization state machine for realigning four channels jesd204a 0.3125 (2) to 3.125 custom phy ip core with preset feature custom phy ip core with preset feature notes to table 1?9 : (1) pcie gen2 is supported only for cyclone v gt devices. (2) the 0.27-gbps and 0.3125-gbps data rates are supported using o versampling user logic that you mu st implement in the fpga fab ric. (3) high-voltage output mode (1000-base-cx) is not supported. (4) pending characterization. table 1?9. pcs features of the transceivers in cyclone v devices (part 2 of 2) pcs support data rates (gbps) transmitter datapath receiver datapath
chapter 1: overview for cyclone v device family 1?11 pcie gen1 and gen2 hard ip february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet pcie gen1 and gen2 hard ip cyclone v gx, gt, sx, and st devices contai n pcie hard ip?consisting of the mac, data link, and transaction layers?that is de signed for performance, ease-of-use, and increased functionality. the pcie hard ip supports pcie gen2 end point and root port for x1 and x2 lanes configuration, and gen1 end point and root port for up to x4 lane configuration. the pcie endpoint support includes multifun ction support for up to eight functions, as shown in figure 1?2 . the integrated multifunction support reduces the fpga logic requirements by up to 20 k les for pcie designs that require multiple peripherals. the cyclone v pcie hard ip operates independently from the core logic. this independent operation allows the pcie link to wake up and complete link training in less than 100 ms while the cy clone v device completes lo ading the programming file for the rest of the device. in addition, the pcie hard ip in the cyclone v device provides improved end-to-end datapath protection using ecc. fpga gpios cyclone v devices offer highly configurable gpios. the following list describes the many features of the gpios: programmable bus hold and weak pull-up. lvds output buffer with programmabl e differential output voltage (v od ) and programmable pre-emphasis. dynamic on-chip parallel termination (r t oct) for all i/o banks with oct calibration to limit the termination impedance variation to 15%. on-chip dynamic termination that has th e ability to swap between serial and parallel termination, depending on whether there is read or write on a common bus for signal integrity. unused voltage reference ( vref ) pins that can be configured as user i/os. easy timing closure support using the hard read fifo in the input register path, and delay-locked loop (dll) delay chai n with fine and coarse architecture. figure 1?2. pcie multifunction for cyclone v devices cyclone v device pcie link host cpu memory controller root complex local peripheral 1 local peripheral 2 pcie rp pcie ep can gbe ata bridge to pcie sp1 gpio 12c usb external system
1?12 chapter 1: overview for cyclone v device family external memory cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet external memory cyclone v devices support up to two ha rd memory controllers for ddr3, ddr2, lpddr2, and lpddr sdram devices. each controller supports 8- to 32-bit components of up to 4 gigabits (gb) in de nsity with two chip selects and optional ecc. cyclone v devices also support soft memory controllers for ddr3, ddr2, lpddr2, and lpddr sdram fo r maximum flexibility. table 1?10 lists the performance of the external memory interface in cyclone v devices. adaptive logic module cyclone v devices use a 28-nm alm as the ba sic building block of the logic fabric. the alm, as shown in figure 1?3 , uses an 8-input fractu rable look-up table (lut) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packin g capability than previous generations. you can configure up to 25% of the alms in cyclone v devi ces as distributed memory using mlabs. for more information, refer to ?embedded memory? on page 1?14 . table 1?10. external memory interface performance in cyclone v devices interface voltage (v) hard controller (mhz) soft controller (mhz) ddr3 sdram 1.5 400 300 ddr3l sdram 1.35 400 300 ddr3u sdram 1.25 333 300 ddr2 sdram 1.8 400 300 1.5 400 300 lpddr2 sdram 1.2 333 300 lpddr sdram 1.8 200 200 figure 1?3. alm for cyclone v devices cyclone v device 1 2 3 4 5 6 7 8 adaptive lut full adder reg reg full adder reg reg
chapter 1: overview for cyclone v device family 1?13 variable-precision dsp block february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet variable-precision dsp block cyclone v devices feature a variable-precisi on dsp block that you can configure to support signal processing with precisions ranging from 9 x 9, 18 x 19, and 27 x 27 bits natively. you can configure each dsp block during co mpilation as independent three 9 x 9, two 18 x 19, or one 27 x 27 multipliers. with a dedicated 64-bit cascade bus, you can cascade multiple variable-precision dsp blocks to implement even higher precision dsp functions efficiently. the variable-precision dsp bloc k also supports these features: a 64-bit accumulator that is the largest in the industry. a hard preadder that is availabl e in both 18- and 27-bit modes. cascaded output adders for efficient systolic finite impulse response (fir) filters. internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode. fully independent multiplier operation. a second accumulator feedback re gister to accommodate complex multiply-accumulate functions. efficient support for single- and double -precision floating point arithmetic. the inferability of all modes by the quartus ? ii design software. table 1?11 lists the relevant dsp block conf igurations for a few usage examples. table 1?12 lists the variable-precision dsp resources by bit precision for each cyclone v device. table 1?11. variable-precision dsp block configurations for cyclone v devices usage multiplier size (bit) dsp block resource low precision fixed point for video applications three 9 x 9 1 variable-precision dsp block medium precision fixed point in fir filters two 18 x 19 1 variable-precision dsp block fir filters and general dsp usage two 18 x 19 with accumulate 1 variable-precision dsp block high precision fixed- or floating-point implementations one 27 x 27 with accumulate 1 variable-precision dsp block table 1?12. number of multipliers in cyclone v devices (part 1 of 2) variant device variable- precision dsp block independent input and output multiplications operator 18 x 19 multiplier adder mode 18 x 18 multiplier adder summed with 36-bit input 9x9 multiplier 18 x 19 multiplier 27 x 27 multiplier cyclone v e 5cea2257550252525 5cea4 72 216 144 72 72 72 5cea5 124 372 248 124 124 124 5cea7 156 468 312 156 156 156 5cea9 342 1,026 684 342 342 342
1?14 chapter 1: overview for cyclone v device family embedded memory cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet embedded memory the cyclone v embedded memory blocks ar e flexible and designed to provide an optimal amount of small- an d large-sized memory arrays . cyclone v devices contain two types of embedded memory blocks: 640-bit mlab blocks?ideal for wide and shallow memory arrays. the mlab operates at up to 300 mhz. 10-kb m10k blocks?ideal for larger memory arrays while still providing a large number of independent ports. the m10k embedded memory operates at up to 380 mhz. cyclone v gx 5cgxc3 42 126 84 42 42 42 5cgxc4 70 210 140 70 70 70 5cgxc5 124 372 248 124 124 124 5cgxc7 156 468 312 156 156 156 5cgxc9 342 1,026 684 342 342 342 cyclone v gt 5cgtd5 124 372 248 124 124 124 5cgtd7 156 468 312 156 156 156 5cgtd9 342 1,026 684 342 342 342 cyclone v se 5csea2 36 108 73 36 36 36 5csea4 58 174 116 58 58 58 5csea5 87 261 173 87 87 87 5csea6 112 336 224 112 112 112 cyclone v sx 5csxc4 36 108 73 36 36 36 5csxc5 58 174 116 58 58 58 5csxc6 87 261 173 87 87 87 cyclone v st 5cstd5 87 261 173 87 87 87 5cstd6 112 336 224 112 112 112 table 1?12. number of multipliers in cyclone v devices (part 2 of 2) variant device variable- precision dsp block independent input and output multiplications operator 18 x 19 multiplier adder mode 18 x 18 multiplier adder summed with 36-bit input 9x9 multiplier 18 x 19 multiplier 27 x 27 multiplier
chapter 1: overview for cyclone v device family 1?15 dynamic and partial reconfiguration february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 1?13 lists the supported memory conf igurations for cyclone v devices. dynamic and partial reconfiguration the dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, pma settings, or prot ocols of a channel, wi thout affecting data transfer on adjacent channels. this feature is ideal for applications that require on-the-fly multiprotocol or multirate support. you can reconfigure the pma and pcs blocks with dynamic reconfiguration. partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain operational. this capabili ty is important in systems with critical uptime requirements because it allows you to make updates or adjust functionality without disrupting services. apart from lowering cost and power consum ption, partial reconfiguration increases the effective logic density of the device be cause placing device fu nctions that do not operate simultaneously is not necessary. instead, you can store these functions in external memory and load them whenever th e functions are required. this capability reduces the size of the device because it allows multiple applications on a single device?saving the board space and reducing the power consumption. altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the proven incrementa l compile and design flow in the quartus ii design software. with the altera ? solution, you do not need to know all the intricate device architecture details to perform a partial reconfiguration. partial reconfiguration is supported throug h the fpp x16 configuration interface. you can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration of both the device core and transceivers. clock networks and pll clock sources the cyclone v clock network architecture is based on altera?s proven global, quadrant, and peripheral clock structure, wh ich is supported by dedicated clock input pins and fractional plls. cyclone v devices have 16 global clock networks capable of up to 550 mhz operation. the quartus ii softwa re identifies all unused sections of the clock network and powers them down , which reduces power consumption. table 1?13. embedded memory block configurations for cyclone v devices memory block depth (bits) programmable widths mlab 32 x1, x2, x4, x8, x9, x10, x16, x18, or x20 m10k 256 x40 or x32 512 x20 or x16 1k x10 or x8 2k x5 or x4 4k x2 8k x1
1?16 chapter 1: overview for cyclone v device family enhanced configuration and configuration via protocol cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet cyclone v devices have up to eight plls, each with nine output counters that you can use to reduce pll usage in two ways: reduce the number of oscillators that are required on your board by using fractional plls. reduce the number of clock pins that ar e used in the device by synthesizing multiple clock frequencies from a single reference clock source. cyclone v devices use a fractional pll arch itecture in addition to the historical integer pll. if you use the fractional pll mode, you can use the plls for precision fractional-n frequency synthesis?removing the need for off-chip reference clock sources in your design. the transceiver fractional plls that are not used by the transceiver i/os can be used as general purpose fractional plls by the fpga fabric. apart from frequency synthesis, on-chip clock deskew, jitter attenuation, counter reconfiguration, programmable output cl ock duty cycles, pll cascading, and reference clock switchover, the plls in the cyclone v devices also support the following key features: programmable bandwidth user-mode reconfiguration of plls low power mode for each fractional pll reference clock switchover dynamic phase shift direct, source synchronous, zdb, exte rnal feedback, and lvds compensation enhanced configuration and co nfiguration via protocol cyclone v devices support 3.3-v programmi ng voltage and several configuration modes. table 1?14 lists the configuration modes and features supported by the cyclone v devices. table 1?14. configuration modes and features for cyclone v devices mode data width (bit) maximum clock rate (mhz) maximum data rate (mbps) decompression design security remote system update partial reconfiguration as through the epcs and epcq serial configuration device x1, x4 80 ? vvv ? ps through cpld or external microcontroller x1 125 125 vv ?? fpp x8, x16 125 ? vv parallel flash loader 16-bit only cvp (pcie) x1, x2, x4 (1) ?? ? vv v jtag x1 33 33 ? ? ? note to table 1?14 : (1) the number of lanes instead of bit.
chapter 1: overview for cyclone v device family 1?17 power management february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet instead of using an external flash or ro m, you can configure the cyclone v devices through pcie using cvp. the cvp mode of fers the fastest configuration rate and flexibility with the easy-to-use pcie hard ip block interface. the cyclone v cvp implementation conforms to the pcie 10 0 ms power-up-to-active time requirement. power management leveraging the fpga architectural features , process technology advancements, and transceivers that are designed for power efficiency, the cyclone v devices consume less power than previous generation cyclone fpgas: total device core power consumption?less by up to 40%. transceiver channel power consumption?less by up to 50%. additionally, cyclone v device s contain several hard ip blocks that reduce logic resources and deliver substantial power savings of up to 25% less power than equivalent soft implementations. soc fpga with hps each soc fpga combines an fpga fabric and an hps in a single device. this combination delivers the flexibility of programmable logic with the power and cost savings of hard ip in these ways: reduces board space, system power, and bi ll of materials cost by eliminating a discrete embedded processor allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard extends the product life and revenue th rough in-field hardware and software updates
1?18 chapter 1: overview for cyclone v device family soc fpga with hps cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet features of the hps the hps consists of a dual-core arm cort ex-a9 mpcore processor, a rich set of peripherals, and a shared multiport sd ram memory controller, as shown in figure 1?4 . system peripherals each ethernet mac, usb otg, nand flash controller, and sd/mmc/sdio controller module has an integrated dma controller. for modules without an integrated dma controller, an additional dma controller module provides up to eight channels of high-bandwidth data transfers. the debug access port provides interfaces to industry standard jtag debug probes and supports arm coresight debug and core traces to facilitate software development. figure 1?4. hps with dual-core arm cortex-a9 mpcore processor fpga fabric hps hps-to-fpga lightweight hps-to-fpga fpga-to-hps fpga-to-hps sdram configuration controller fpga manager 64 kb on-chip ram 64 kb boot rom level 3 interconnect ethernet mac (2x) usb otg (2x) nand flash controller sd/mmc/sdio controller dma controller etr (trace) debug access port arm cortex-a9 mpcore cpu0 (arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit) cpu1 (arm cortex-a9 with neon/fpu, 32 kb instruction cache, 32 kb data cache, and memory management unit) scu acp l2 cache (512 kb) multiport ddr sdram controller with optional ecc low speed peripherals (timers, gpios, uart, spi, i2c, can, quad spi flash controller, system manager, clock manager, reset manager, and scan manager)
chapter 1: overview for cyclone v device family 1?19 soc fpga with hps february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet hps?fpga axi bridges the hps?fpga bridges, which suppor t the advanced mi crocontroller bus architecture (amba ? ) advanced extensible interface (axi ? ) specifications, consist of the following bridges: fpga-to-hps axi bridge?a high-performance bus supporting 32-, 64-, and 128-bit data widths that allows the fpga fa bric to master transactions to the slaves in the hps hps-to-fpga axi bridge?a high-performance bus supporting 32-, 64-, and 128-bit data widths that allows the hps to master transactions to the slaves in the fpga fabric. lightweight hps-to-fpga axi bridge?a lower performance 32-bit width bus that allows the hps to master transactions to the slaves in the fpga fabric. the hps?fpga axi bridges also allow the fpga fabric to access the memory shared by one or both microprocessors, and prov ide asynchronous clock crossing with the clock from the fpga fabric. hps sdram controller subsystem the hps sdram controller subsystem contains a multiport sdram memory controller and ddr phy that are shared between the fpga fabric (through the fpga-to-hps sdram interface), the level 2 (l 2) cache, and the le vel 3 (l3) system interconnect. the fpga-to-hps sdram interface supports amba axi and avalon ? memory-mapped (avalon-mm) interface standards, and provides up to four ports with separate read and write directions. to maximize memory performance, th e sdram controller subsystem supports command and data reordering, deficit ro und-robin arbitration with aging, and high-priority bypass features. the sdram controller subsytem supports ddr2, ddr3, lpddr, or lpddr2 devices up to 4 g b in density and runs up to 400 mhz (800 mbps data rate). for easy migration, the fpga-to-hps sdram interface is compatible with the interface of the soft sdram memory controller ips and hard sdram memory controllers in the fpga fabric. fpga configuration and processor booting the fpga fabric and hps in the soc fpga are powered independently. you can reduce the clock frequencies or gate the cl ocks to reduce dynamic power, or shut down the entire fpga fabric to reduce total system power. you can configure the fpga fabric and boot the hps independently, in any order, providing you with more design flexibility: you can boot the hps before you power up and configure the fpga fabric. after the system is running, the hps reconfigur es the fpga fabric at any time under program control or through the fpga configuration controller. you can power up both the hps and the fpga fabric together, configure the fpga fabric first, and then upload the boot code to the hps from the fpga fabric.
1?20 chapter 1: overview for cyclone v device family soc fpga with hps cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet hardware and software development for hardware development, you can configure the hps and connect your soft logic in the fpga fabric to the hps interfaces usin g the qsys system integration tool in the quartus ii software. for software development, the arm-base d soc fpga devices inherit the rich software development ecosystem available for the arm cortex-a9 mpcore processor. the software development process for altera soc fpgas follows the same steps as those for other soc devices. altera also provides support for the linux and vxworks ? operating systems. you can begin device-specifi c firmware and software development on the altera soc fpga virtual target. the virtual target is a fast pc-based functional simulation of a target development system?a model of a complete development board that runs on a pc. the virtual target enables the de velopment of device-specific production software that can run unmodified on actual hardware.
chapter 1: overview for cyclone v device family 1?21 ordering information february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet ordering information figure 1?5 and figure 1?6 show sample ordering codes and list the options available for cyclone v e, gx, and gt devices. figure 1?5. ordering information for cyclone v e devices? preliminary family signature embedded hard ips package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method e : enhanced logic/memory b : no hard pcie or hard memory controller f : no hard pcie and maximum 2 hard memory controllers 5c : cyclone v f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 17 : 256 pins 23 : 484 pins 27 : 672 pins 31 : 896 pins ubga package type 15 : 324 pins 19 : 484 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging 5c e f a9 f 31 c 7 n member code family variant a2 : 25,000 logic elements a4 : 48,000 logic elements a5 : 76,500 logic elements a7 : 149,500 logic elements a9 : 301,000 logic elements figure 1?6. ordering information for cyclone v gx and gt devices? preliminary family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method gx : 3-gbps transceivers gt : 5-gbps transceivers b : no hard pcie or hard memory controller f : maximum 2 hard pcie and 2 hard memory controllers 5c : cyclone v gx variant c3 : 31,000 logic elements c4 : 50,000 logic elements c5 : 76,500 logic elements c7 : 149,500 logic elements c9 : 301,000 logic elements gt variant d5 : 76,500 logic elements d7 : 149,500 logic elements d9 : 301,000 logic elements b : 3 c : 6 d : 9 e : 12 5 : 5 gbps 6 : 3.125 gbps 7 : 2.5 gbps f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 23 : 484 pins 27 : 672 pins 31 : 896 pins 35 : 1,152 pins ubga package type 15 : 324 pins 19 : 484 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging 5c gt f d9 e 5 f35c7 n member code family variant
1?22 chapter 1: overview for cyclone v device family ordering information cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet figure 1?7 and figure 1?8 show sample ordering codes and list the options available for cyclone v se, sx, and st devices. ? figure 1?7. ordering information for cyclone v se devices? preliminary family signature embedded hard ips package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment metho d se : soc fpga with enhanced logic/memory 5c : cyclone v f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 31 : 896 pins ubga package type 19 : 484 pins 23 : 672 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 processor cores 1 : single-core 2 : dual-core n : lead-free packaging es : engineering sample 5c se m a6 f 31 c 6 2 n member code family variant a2 : 25,000 logic elements a4 : 40,000 logic elements a5 : 85,000 logic elements a6 : 110,000 logic elements b : no hard pcie or hard memory controller m : no hard pcie and 1 hard memory controller figure 1?8. ordering information for cyclone v sx and st devices? preliminary family signature embedded hard ips transceiver count transceiver speed grade package type package code operating temperature fpga fabric speed grade optional suffix indicates specific device options or shipment method sx : soc fpga with 3-gbps transceivers st : soc fpga with 5-gbps transceivers m : no hard pcie and 1 hard memory controller f : maximum 2 hard pcie controllers and 1 hard memory controller 5c : cyclone v sx variant c4 : 40,000 logic elements c5 : 85,000 logic elements c6 : 110,000 logic elements st variant d5 : 85,000 logic elements d6 : 110,000 logic elements c : 6 d : 9 4 : 5 gbps 6 : 3.125 gbps f : fineline bga (fbga) u : ultra fineline bga (ubga) fbga package type 31 : 896 pins ubga package type 23 : 672 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 n : lead-free packaging es : engineering sample 5c st f d6 d 4 f31c 62 n member code family variant processor cores 2 : dual-core
chapter 1: overview for cyclone v device family 1?23 document revision history february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet document revision history table 1?15 lists the revision history for this document. table 1?15. document revision history date version changes february 2012 1.2 updated table 1?2 , table 1?3 , and table 1?6 . updated ?cyclone v family plan? on page 1?4 and ?clock networks and pll clock sources? on page 1?15 . updated figure 1?1 and figure 1?6 . november 2011 1.1 updated table 1?1, table 1?2, table 1?3, table 1?4, table 1?5, and table 1?6. updated figure 1?4, figure 1?5, figure 1?6, figure 1?7, and figure 1?8. updated ?system peripherals? on page 1?18, ?hps?fpga axi bridges? on page 1?19, ?hps sdram controller subsystem? on page 1?19, ?fpga configuration and processor booting? on page 1?19, and ?hardware and software development? on page 1?20. minor text edits. october 2011 1.0 initial release.
1?24 chapter 1: overview for cyclone v device family document revision history cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet
cv-51002-1.2 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone v device handbook volume 1: device overview and datasheet february 2012 subscribe iso 9001:2008 registered 2. device datasheet for cyclone v devices this chapter describes the electrical charac teristics, switching characteristics, and configuration specifications for cyclone ? v devices. electrical characteristics include operating conditions and power consumption. switching characteristics list the transceiver specifications, and core an d periphery performance. configuration specifications cover power-on reset (por) specifications, various configuration mode timing parameters, remote system upgrad es timing, and user watchdog internal oscillator frequency specification. this chapter also describes i/o timing, including programmable i/o element (ioe) delay and programmable output buffer delay. f for more information about the densities an d packages of devices in the cyclone v family, refer to the overview for cyclone v device family chapter. electrical characteristics the following sections describe the electr ical characteristics of cyclone v devices. operating conditions cyclone v devices are rated according to a se t of defined parameters. to maintain the highest possible performance and reliability of the cyclone v devices, you must consider the operating requirements described in this chapter. cyclone v devices are offered in commercial and industrial grades. commercial devices are offered in ?6 (fastest), ?7, an d ?8 speed grades. industrial and automotive devices are offered in the ?7 speed grade. absolute maximum ratings absolute maximum ratings define the maxi mum operating conditions for cyclone v devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. c conditions other than those listed in table 2?1 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have ad verse effects on the device. february 2012 cv-51002-1.2
2?2 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?1 lists the cyclone v absolute maximum ratings. maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage listed in table 2?2 and undershoot to -2.0 v for input currents le ss than 100 ma and periods shorter than 20 ns. table 2?2 lists the maximum allowed input oversh oot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percenta ge of high time over the lifetime of the device. a dc signal is equivalent to 100% duty cycle. for example, a signal that overshoots to 3.95 v can only be at 3.95 v fo r ~5% over the lifetime of the device; for a device lifetime of 10 years, this amounts to half a year. table 2?1. absolute maximum ratings for cyclone v devices?preliminary symbol description minimum maximum unit v cc core voltage and periphery circuitry power supply ?0.5 1.35 v v ccpgm configuration pins power supply ?0.5 3.75 v v cc_aux auxiliary supply ?0.5 3.75 v v ccbat battery back-up power supply for design security volatile key register ?0.5 3.75 v v ccpd i/o pre-driver power supply ?0.5 3.75 v v ccio i/o power supply ?0.5 3.9 v v cca_fpll pll analog power supply ?0.5 3.75 v v cch_gxb transceiver high voltage power ?0.5 3.75 v v cce_gxb transceiver power ?0.5 1.21 v v ccl_gxb clock network power ?0.5 1.21 v v i dc input voltage ?0.5 4 v i out dc output current per pin ?25 40 ma t j operating junction temperature ?55 125 c t stg storage temperature (no bias) ?65 150 c table 2?2. maximum allowed overshoot during transitions for cyclone v devices?preliminary symbol description condition (v) overshoot duration as % of high time unit vi (ac) ac input voltage 3.7 100 % 3.75 59.79 % 3.8 33.08 % 3.85 18.45 % 3.9 10.36 % 3.95 5.87 % 43.34% 4.05 1.92 % 4.1 1.11 %
chapter 2: device datasheet for cyclone v devices 2?3 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet recommended operating conditions recommended operating conditions are the functional operation limits for the ac and dc parameters for cyclone v devices. table 2?3 lists the steady-state voltage values expected from cyclone v devices. power supply ramps must all be strictly monotonic, without plateaus. table 2?3. recommended operating conditions for cyclone v devices?preliminary symbol description condition minimum typical maximum unit v cc core voltage, periphery circuitry power supply, transceiver physical coding sublayer (pcs) power supply, and transceiver pci express ? (pcie ? ) hard ip digital power supply ? 1.07 1.1 1.13 v v cc_aux auxiliary supply ? 2.375 2.5 2.625 v v ccpd i/o pre-driver (3.3 v) pow er supply ? 3.135 3.3 3.465 v i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) pow er supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.3 v) power supply ? 3.135 3.3 3.465 v i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.35 v) power supply ? 1.283 1.35 1.418 v i/o buffers (1.25 v) power supply ? 1.19 1.25 1.31 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.3 v) power supply ? 3.135 3.3 3.465 v configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_fpll (1) pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccbat (2) battery back-up power supply (for design security volatile key register) ?1.2?3.0v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c automotive ?40 ? 125 c
2?4 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?4 lists the transceiver power supply recommended operating conditions for cyclone v gx devices. table 2?5 lists the steady-state voltage values expected from cyclone v system-on-a-chip (soc) fpga with arm ? -based hard processor system (hps). power supply ramps must all be strictly monotonic, without plateaus. t ramp power supply ramp time standard por (porsel=0) 200 s ? 100 ms ? fast por (porsel=1) 200 s ? 4 ms ? notes to table 2?3 : (1) pll digital voltage is regulated from v cca_fpll . (2) if you do not use the design security feature in cyclone v devices, connect v ccbat to a 1.5-v, 2.5-v, or 3.0-v power supply. the power-on reset (por) circuitry monitors v ccbat . cyclone v devices do not exit por if v ccbat stays low. table 2?3. recommended operating conditions for cyclone v devices?preliminary symbol description condition minimum typical maximum unit table 2?4. transceiver power supply operating conditions for cyclone v gx devices?preliminary symbol description minimum typical maximum unit v cch_gxbl transceiver high voltage power (left side) 2.375 2.5 2.625 v v cce_gxbl transmitter and receiver power (left side) 1.07 1.1 1.13 v v ccl_gxbl clock network power (left side) 1.07 1.1 1.13 v table 2?5. hps power supply operating conditions for cyclone v se, sx, and st devices?preliminary symbol description minimum typical maximum unit v cc_hps hps core voltage and periphery circuitry power supply 1.07 1.1 1.13 v v ccpd_hps hps i/o pre-driver (3.3 v) power supply 3.135 3.3 3.465 v hps i/o pre-driver (3.0 v) power supply 2.85 3.0 3.15 v hps i/o pre-driver (2.5 v) power supply 2.375 2.5 2.625 v v ccio_hps hps i/o buffers (3.3 v) power supply 3.135 3.3 3.465 v hps i/o buffers (3.0 v) power supply 2.85 3.0 3.15 v hps i/o buffers (2.5 v) power supply 2.375 2.5 2.625 v hps i/o buffers (1.8 v) power supply 1.71 1.8 1.89 v hps i/o buffers (1.5 v) power supply 1.425 1.5 1.575 v hps i/o buffers (1.2 v) power supply 1.14 1.2 1.26 v v ccrstclk_hps hps reset and clock input pins (3.3 v) power supply 3.135 3.3 3.465 v hps reset and clock input pins (3.0 v) power supply 2.85 3.0 3.15 v hps reset and clock input pins (2.5 v) power supply 2.375 2.5 2.625 v hps reset and clock input pins (1.8 v) power supply 1.71 1.8 1.89 v v ccpll_hps hps pll analog voltage regulator power supply 2.375 2.5 2.625 v
chapter 2: device datasheet for cyclone v devices 2?5 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet dc characteristics this section lists the supply current, i/o pin leakage current, input pin capacitance, on-chip termination tolerance, and hot socketing specifications. supply current standby current is the current drawn from the respective power rails used for power budgeting. use the excel-based early po wer estimator (epe) to estimate supply current for your design because these currents vary greatly with the resources you use. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . i/o pin leakage current table 2?6 lists the cyclone v i/o pin leakage current specifications. bus hold specifications table 2?7 lists the cyclone v device bus hold specifications. table 2?6. i/o pin leakage current for cyclone v devices?preliminary symbol description conditions min typ max unit i i input pin v i = 0 v to v cciomax ?30 ? 30 a i oz tri-stated i/o pin v o = 0 v to v cciomax ?30 ? 30 a table 2?7. bus hold parameters for cyclone v devices?preliminary (part 1 of 2) (1) parameter symbol conditions v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus-hold, low, sustaining current i susl v in > v il (max.) 8 ? 12 ? 30?50?70?70?a bus-hold, high, sustaining current i sush v in < v ih (min.) ?8 ? ?12 ? ?30 ? ?50 ? ?70 ? ?70 ? a bus-hold, low, overdrive current i odl 0v < v in < v ccio ? 125 ? 175 ? 200 ? 300 ? 500 ? 500 a bus-hold, high, overdrive current i odh 0v < v in < v ccio ? ?125 ? ?175 ? ?200 ? ?300 ? ?500 ? ?500 a
2?6 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet on-chip termination (oct) specifications if you enable oct calibration, calibration is automatically performed at power up for i/o pins connected to the calibration block. calibration accuracy for the calibrated on-chip series termination (r s oct) and on-chip parallel termination (r t oct) are applicable at the moment of calibration. when process, voltage, and temperature (pvt) conditions change after calibration, the tolerance may change. bus-hold trip point v trip ? 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 v note to table 2?7 : (1) the bus-hold trip points are based on calc ulated input voltages fr om the jedec standard. table 2?7. bus hold parameters for cyclone v devices?preliminary (part 2 of 2) (1) parameter symbol conditions v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max
chapter 2: device datasheet for cyclone v devices 2?7 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?8 lists the cyclone v oct termination calibration accuracy specifications. table 2?8. oct calibration accuracy specifications for cyclone v devices?preliminary (1) symbol description conditions (v) calibration accuracy unit c6 speed grade c7, i7 speed grade c8, a7 speed grade 25- r s internal series termination with calibration (25- setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 50- r s internal series termination with calibration (50- setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % 34- and 40- r s internal series termination with calibration (34- and 40- setting) v ccio = 1.5, 1.35, 1.25, 1.2 15 15 15 % 48- , 60 - , and 80- r s internal series termination with calibration (48- , 60- , and 80- setting) v ccio = 1.2 15 15 15 % 50- r t internal parallel termination with calibration (50- setting) v ccio = 2.5, 1.8, 1.5, 1.2 -10 to +40 -10 to +40 -10 to +40 % 20- , 30- , 40- , 60- , and 120- r t internal parallel termination with calibration (20- , 30- , 40- , 60- , and 120- setting) v ccio = 1.5, 1.35, 1.25 -10 to +40 -10 to +40 -10 to +40 % 60- and 120- r t internal parallel termination with calibration (60- and 120- setting) v ccio = 1.2 -10 to +40 -10 to +40 -10 to +40 % 25- r s_left_shift internal left shift series termination with calibration (25- r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 15 15 15 % note to table 2?8 : (1) oct calibration accuracy is valid at the time of calibration only.
2?8 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?9 lists the cyclone v oct without calibration resistance tolerance to pvt changes. oct calibration is automatically performe d at power up for the oct-enabled i/o pins. table 2?10 lists oct variation with temper ature and voltage after power-up calibration. use table 2?10 to determine the oct variation after power-up calibration and equation 2?1 to determine the oct variation without recalibration. table 2?9. oct without calibration resistance tolerance specifications for cyclone v devices?preliminary symbol description conditions (v) resistance tolerance unit c6 speed grade c7, i7 speed grade c8, a7 speed grade 25- r s internal series termination without calibration (25- setting) v ccio = 3.0 and 2.5 30 40 40 % 25- r s internal series termination without calibration (25- setting) v ccio = 1.8 and 1.5 30 40 40 % 25- r s internal series termination without calibration (25- setting) v ccio = 1.2 35 50 50 % 50- r s internal series termination without calibration (50- setting) v ccio = 3.0 and 2.5 30 40 40 % 50- r s internal series termination without calibration (50- setting) v ccio = 1.8 and 1.5 30 40 40 % 50- r s internal series termination without calibration (50- setting) v ccio = 1.2 35 50 50 % 100- r d internal differential termination (100- setting) v ccio = 2.5 25 tbd tbd % equation 2?1. oct variation without recalibration?preliminary (1) , (2) , (3) , (4) , (5) , (6) notes to equation 2?1 : (1) the r oct value calculated from equation 2?1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) t is the variation of temperature with respect to the temperature at power up. (4) v is the variation of voltage with respect to v ccio at power up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. r oct r scal 1 dr dt ------ - t ?? dr dv ------- v ?? + ?? ?? =
chapter 2: device datasheet for cyclone v devices 2?9 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?10 lists the oct variation after the power-up calibration. pin capacitance table 2?11 lists the cyclone v device family pin capacitance. hot socketing table 2?12 lists the hot socketing specifications for cyclone v devices. table 2?10. oct variation after power-up calibration for cyclone v devices?preliminary (1) symbol description v ccio (v) typical unit dr/dv oct variation with voltage without recalibration 3.0 0.0297 %/mv 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 dr/dt oct variation with temperature without recalibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 note to table 2?10 : (1) valid for a v ccio range of 5% and a temperature range of 0 to 85c. table 2?11. pin capacitance for cyclone v devices symbol description value unit c iotb input capacitance on top and bottom i/o pins 5.5 pf c iolr input capacitance on left and right i/o pins 5.5 pf c outfb input capacitance on dual-purpose clock output and feedback pins 5.5 pf table 2?12. hot socketing specifications for cyclone v devices?preliminary symbol description maximum i iopin (dc) dc current per i/o pin 300 a i iopin (ac) ac current per i/o pin 8 ma (1) i xcvr-tx (dc) dc current per transceiver transmitter (tx) pin 100 ma i xcvr-rx (dc) dc current per transceiver receiver (rx) pin 50 ma note to table 2?12 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate.
2?10 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet internal weak pull-up resistor table 2?13 lists the weak pull-up resistor values for cyclone v devices. i/o standard specifications table 2?14 through table 2?19 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by cyclone v devices. th ese tables also list the cyclone v device family i/o standard specifications. the v ol and v oh values are valid at the corresponding i oh and i ol , respectively. for an explanation of terms used in table 2?14 through table 2?19 , refer to ?glossary? on page 2?37 . table 2?13. internal weak pull-up resistor values for cyclone v devices?preliminary (1) , (2) symbol description conditions (v) (3) typ (4) unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. v ccio = 3.3 5% 25 k v ccio = 3.0 5% 25 k v ccio = 2.5 5% 25 k v ccio = 1.8 5% 25 k v ccio = 1.5 5% 25 k v ccio = 1.35 5% 25 k v ccio = 1.25 5% 25 k v ccio = 1.2 5% 25 k notes to table 2?13 : (1) all i/o pins have an option to enable weak pull- up except the configuration, test, and jtag pins. (2) the internal weak pull-down feature is only available for the jtag tck pin. the typical value for this in ternal weak pull-down resistor is approximately 25 k . (3) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . (4) these specifications are valid with 10% tolerances to cover changes over pvt. table 2?14. single-ended i/o standards for cyclone v devices?preliminary (part 1 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min 3.3-v lvttl 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3-v lvcmos 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 2 ?2 3.0-v lvttl 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.4 2.4 2 ?2 3.0-v lvcmos 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 0.1 ?0.1 3.0-v pci 2.85 3 3.15 ? 0.3 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 x v ccio 0.5 x v ccio v ccio + 0.3 0.1 x v ccio 0.9 x v ccio 1.5 ?0.5 2.5 v 2.375 2.5 2.625 ?0.3 0.7 1.7 3.6 0.4 2 1 ?1 1.8 v 1.71 1.8 1.89 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.45 v ccio ? 0.45 2 ?2
chapter 2: device datasheet for cyclone v devices 2?11 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet 1.5 v 1.425 1.5 1.575 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 1.2 v 1.14 1.2 1.26 ?0.3 0.35 x v ccio 0.65 x v ccio v ccio + 0.3 0.25 x v ccio 0.75 x v ccio 2?2 table 2?14. single-ended i/o standards for cyclone v devices?preliminary (part 2 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min table 2?15. single-ended sstl and hstl i/o reference voltage specifications for cyclone v devices?preliminary i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio v ref ? 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl 135 class i, ii 1.283 1.35 1.418 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio sstl 125 class i, ii 1.19 1.25 1.26 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 x v ccio 0.5 x v ccio 0.53 x v ccio ?v ccio /2 ? hsul-12 1.14 1.2 1.3 0.49 x v ccio 0.5 x v ccio 0.51 x v ccio ??? table 2?16. single-ended sstl and hstl i/o standards signal specifications for cyclone v devices?preliminary (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.608 v tt + 0.608 8.1 ?8.1 sstl-2 class ii ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.81 v tt + 0.81 16.2 ?16.2 sstl-18 class i ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 v tt ? 0.603 v tt + 0.603 6.7 ?6.7 sstl-18 class ii ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 0.28 v ccio ? 0.28 13.4 ?13.4 sstl-15 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 8?8 sstl-15 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 x v ccio 0.8 x v ccio 16 ?16 sstl 135 ?v ref ? 0.09 v ref + 0.09 ? v ref ? 0.16 v ref + 0.16 tbd (1) tbd (1) tbd (1) tbd (1)
2?12 chapter 2: device datasheet for cyclone v devices electrical characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet sstl 125 ?v ref ? 0.85 v ref + 0.85 ? v ref ? 0.15 v ref + 0.15 tbd (1) tbd (1) tbd (1) tbd (1) hstl-18 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-18 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-15 class i ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8 ?8 hstl-15 class ii ?v ref ? 0.1 v ref + 0.1 ? v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-12 class i ?0.1 5 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 8?8 hstl-12 class ii ?0.1 5 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25 x v ccio 0.75 x v ccio 16 ?16 hsul-12 ?v ref ? 0.13 v ref + 0.13 ? v ref ? 0.22 v ref + 0.22 0.1 x v ccio 0.9 x v ccio tbd (1) tbd (1) note to table 2?16 : (1) pending silicon characterization. table 2?16. single-ended sstl and hstl i/o standards signal specifications for cyclone v devices?preliminary (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min table 2?17. differential sstl i/o standards for cyclone v devices?preliminary i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 ? 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 ? 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ?0.2 -0.15 ? 0.15 ?0.35 0.35 ? v ccio /2 ? sstl 135 1.283 1.35 1.45 0.2 ?0.2 v ref ? 0.135 v ccio /2 v ref + 0.135 tbd (1) tbd (1) v ref ? 0.15 ? v ref + 0.15 sstl 125 1.19 1.25 1.31 tbd (1) ? tbd (1) v ccio /2 tbd (1) tbd (1) ? tbd (1) tbd (1) tbd (1) note to table 2?17 : (1) pending silicon characterization.
chapter 2: device datasheet for cyclone v devices 2?13 electrical characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet power consumption altera offers two ways to estimate power consumption for a design?the excel-based early power estimator (epe) and the quartus ? ii powerplay power analyzer feature. 1 you typically use the interactive excel-based epe before designing the fpga to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook . table 2?18. differential hstl i/o standards for cyclone v devices?preliminary i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5 x v ccio ? 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.3 v ccio + 0.48 hsul-12 1.14 1.2 1.3 0.26 0.26 0.5 x v ccio ? 0.12 0.5 x v ccio 0.5 x v ccio +0.12 0.4 x v ccio 0.5 x v ccio 0.6 x v ccio 0.44 0.44 table 2?19. differential i/o standard specifications for cyclone v devices?preliminary (1) i/o standard v ccio (v) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min max min typ max min typ max pcml transmitter, receiver, and input reference clock pins of high-speed transceivers use the pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 2?20 on page 2?14 . 2.5 v lvds 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.8 0.247 ? 0.6 1.125 1.25 1.375 rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 1.4 0.1 0.2 0.6 0.5 1.2 1.4 mini-lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 1.325 0.25 ? 0.6 1 1.2 1.4 lvpecl 2.375 2.5 2.625 300 ? ? 0.6 1.8 ? ? ? ? ? ? slvs 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.8 ? ? ? ? ? ? notes to table 2?19 : (1) the 1.4-v and 1.5-v pcml transceiver i/o standard specificatio ns are described in ?transceiver performance specifications? on page 2?14 . (2) rl range: 90 rl 110
2?14 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet switching characteristics this section provides performance characte ristics of cyclone v core and periphery blocks for commercial grade devices. these characteristics can be designated as preliminary or final. preliminary characteristics are obtained using simulation results, process data, and other known parameters. the title of these tables show the designation as ?preliminary.? final numbers are based on actual sili con characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no designations on finalized tables. transceiver performance specifications this section describes transceiver performance specifications. table 2?20 lists the cyclone v gx transceiver specifications. table 2?20. transceiver specifications for cyclone v gx devices?preliminary (part 1 of 3) symbol/ description conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2 v pcml, 1.5 v pcml, 2.5 v pcml, differential lvpecl (1) , hcsl , and lvds input frequency from refclk input pins ? 27 ? 550 27 ? 550 27 ? 550 mhz duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 2000 200 ? 2000 200 ? 2000 mv spread-spectrum modulating clock frequency pcie 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0 to ?0.5% ?? 0 to ?0.5% ?? 0 to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? v icm (ac coupled) ? 1.1 (2) 1.1 (2) 1.1 (2) v v icm (dc coupled) hcsl i/o standard for the pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ?
chapter 2: device datasheet for cyclone v devices 2?15 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet transceiver clocks fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz avalon ? memory- mapped (avalon-mm) phy management clock frequency < 150 mhz receiver supported i/o standards 1.5 v pcml, 2.5 v pcml, lvpecl , and lvds data rate ? 614 ? 3125 614 ? 3125 614 ? 2500 mbps absolute v max for a receiver pin (3) ? ? ? 1.2 ? ? 1.2 ? ? 1.2 v absolute v min for a receiver pin ? ?0.4 ? ? ?0.4 ? ? ?0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration ? ? ? 2.2 ? ? 2.2 ? ? 2.2 v minimum differential eye opening at the receiver serial input pins (4) ?85??85??85??mv differential on-chip termination resistors 85 ? setting ? 85 ? ? 85 ? ? 85 ? 100 ? setting ? 100 ? ? 100 ? ? 100 ? 120 ? setting ? 120 ? ? 120 ? ? 120 ? 150- setting ? 150 ? ? 150 ? ? 150 ? differential and common mode return loss pcie gen1, gige compliant ? programmable ppm detector (5) ? 62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm run length ? ? ? 200 ? ? 200 ? ? 200 ui programmable equalization ???4??4??4db programmable dc gain dc gain setting = 0 ?0 ??0 ??0 ? db dc gain setting = 1 ?3 ??3 ??3 ? db table 2?20. transceiver specifications for cyclone v gx devices?preliminary (part 2 of 3) symbol/ description conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max
2?16 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet transmitter supported i/o standards 1.5 v pcml data rate ? 614 ? 3125 614 ? 3125 614 ? 2500 mbps v ocm ? ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85 ? setting ? 85 ? ? 85 ? ? 85 ? 100 ? setting ? 100 ? ? 100 ? ? 100 ? 120 ? setting ? 120 ? ? 120 ? ? 120 ? 150- setting ? 150 ? ? 150 ? ? 150 ? rise time (6) ? 30 ? 160 30 ? 160 30 ? 160 ps fall time (6) ? 30 ? 160 30 ? 160 30 ? 160 ps cmu pll supported data range ? 614 ? 3125 614 ? 3125 614 ? 2500 mbps transceiver-fpga fabric interface interface speed (single-width mode) ? 25 ? 187.5 25 ? 163.84 25 ? 156.25 mhz interface speed (double-width mode) ? 25 ? 163.84 25 ? 163.84 25 ? 156.25 mhz notes to table 2?20 : (1) differential lvpecl signal l evels must comply to the minimu m and maximum peak-to-peak differe ntial input voltage specified i n this table. (2) the reference clock common mo de voltage is equal to the v ccr_gxb power supply level. (3) the device cannot tolerate prolonged operation at this absolute maximum. (4) the differential eye opening specificatio n at the receiver input pins assumes that you have disabled the receiver equalizati on feature. if you enable the receiver equalization feature, th e receiver circuitry can tolerate a lower minimum eye opening, de pending on the equalization l evel. (5) the rate matcher supports only up to 300 parts per million (ppm). (6) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. table 2?20. transceiver specifications for cyclone v gx devices?preliminary (part 3 of 3) symbol/ description conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max
chapter 2: device datasheet for cyclone v devices 2?17 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?21 lists the cyclone v gx transceiver block jitter specifications. table 2?21. transceiver block jitter specifications for cyclone v gx devices?preliminary symbol/ description conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max pcie transmit jitter generation (1) total jitter at 2.5 gbps (gen1) compliance pattern ? ? 0.25 ? ? 0.25 ? ? 0.25 ui pcie receiver jitter tolerance (1) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 > 0.6 ui gige transmit jitter generation (2) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ? ? 0.279 ui gige receiver jitter tolerance (2) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 ui notes to table 2?21 : (1) the jitter numbers for pipe are comp liant to the pcie base specification 2.0. (2) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification.
2?18 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), and memory block specifications. clock tree specifications table 2?22 lists the clock tree specifications for cyclone v devices. pll specifications table 2?23 lists the cyclone v pll specifications when operating in the commercial (0 to 85c), industri al (?40 to 100c), and automo tive (?40 to 125c) junction temperature ranges. table 2?22. clock tree performance for cyclone v devices?preliminary performance unit symbol c6 speed grade c7, i7 speed grade c8, a7 speed grade global clock and regional clock 550 550 460 mhz peripheral clock 155 155 155 mhz table 2?23. pll specifications for cyclone v devices?preliminary (1) (part 1 of 3) symbol parameter min typ max unit f in input clock frequency c6 speed grade 5 ? 670 (2) mhz c7, i7 speed grades 5 ? 622 (2) mhz c8, a7 speed grades 5 ? 500 (2) mhz f inpfd integer input clock frequency to the pfd 5 ? 325 mhz f finpfd fractional input clock frequency to the pfd 50 ? tbd (1) mhz f vco pll vco operating range c6 speed grade 600 ? 1600 mhz c7, i7 speed grades 600 ? 1400 mhz c8, a7 speed grades 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock c6 speed grade ? ? 550 (3) mhz c7, i7 speed grades ? ? 550 (3) mhz c8, a7 speed grades ? ? 460 (3) mhz f out_ext output frequency for external clock output c6 speed grade ? ? 667 (3) mhz c7, i7 speed grades ? ? 667 (3) mhz c8, a7 speed grades ? ? 533 (3) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configphase time required to reconfigure phase shift ? ? tbd (1) ? t dyconfigclk dynamic configuration clock ? ? 100 mhz t lock time required to lock from end-of-device configuration or deassertion of areset ?? 1 ms
chapter 2: device datasheet for cyclone v devices 2?19 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (8) ?4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (4) , (5) input clock cycle-to-cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle-to-cycle jitter (f ref < 100 mhz) ? ? 750 ps (p-p) t outpj_dc (6) period jitter for dedicated clock output (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outccj_dc (6) cycle-to-cycle jitter for dedicated clock output (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for dedicated clock output (f out < 100 mhz) ??tbd (1) mui (p-p) t outpj_io (6) , (9) period jitter for clock output on regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for clock output on regular i/o (f out < 100 mhz) ??tbd (1) mui (p-p) t outccj_io (6) , (9) cycle-to-cycle jitter for clock output on regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for clock output on regular i/o (f out < 100 mhz) ??tbd (1) mui (p-p) t outpj_dc_f period jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outccj_dc_f cycle-to-cycle jitter for dedicated clock output in fractional mode ? ? tbd (1) ? t outpj_io_f period jitter for clock output on regular i/o in fractional mode ? ? tbd (1) ? t outccj_io_f cycle-to-cycle jitter for clock output on regular i/o in fractional mode ? ? tbd (1) ? t casc_outpj_dc (6) , (7) period jitter for dedicated clock output in cascaded plls (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100 mhz) ??tbd (1) mui (p-p) table 2?23. pll specifications for cyclone v devices?preliminary (1) (part 2 of 3) symbol parameter min typ max unit
2?20 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet dsp block specifications table 2?24 lists the cyclone v dsp block performance specifications. t drift frequency drift after pfdena is disabled for a duration of 100 s ? ? 10 % dk bit bit number of delta sigma modulator (dsm) ? 24 ? bits k value numerator of fraction tbd (1) 8388608 tbd (1) ? f res resolution of vco frequency (f inpfd =100 mhz) ? 5.96 ? hz notes to table 2?23 : (1) pending silicon characterization. (2) this specification is limited in the qu artus ii software by the i/o m aximum frequency. the maximu m i/o frequency is differen t for each i/o standard. (3) this specification is limited by the lower of the two: i/o f max or f out of the pll. (4) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source < 120 ps. (5) f ref is f in/n when n = 1. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pl l, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a different measurement met hod and are available in table 2?28 on page 2?24 . (7) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59 mhz upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (8) high bandwidth pll settings are not supported in external feedback mode. (9) external memory interface clock output jitter specifications use a different measu rement method, whic h is available in table 2?28 on page 2?24 . table 2?23. pll specifications for cyclone v devices?preliminary (1) (part 3 of 3) symbol parameter min typ max unit table 2?24. dsp block performance specifications for cyclone v devices?preliminary mode performance unit c6 speed grade c7, i7 speed grade c8, a7 speed grade modes using one dsp block independent 9 x 9 multiplication 340 300 260 mhz independent 18 x 19 multiplication 287 250 200 mhz independent 18 x 18 multiplication 287 250 200 mhz independent 27 x 27 multiplication 250 200 160 mhz independent 18 x 25 multiplication 310 250 200 mhz independent 20 x 24 multiplication 310 250 200 mhz two 18 x 19 multiplier adder mode 310 250 200 mhz 18 x 18 multiplier added summed with 36-bit input 310 250 200 mhz modes using two dsp blocks complex 18 x 19 multiplication 310 250 200 mhz two 27 x 27 multiplier adder 250 200 160 mhz four 18 x 19 multiplier adder 310 250 200 mhz
chapter 2: device datasheet for cyclone v devices 2?21 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet memory block specifications table 2?25 lists the cyclone v memory block specifications. periphery performance this section describes periphery performance and the high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the lvds high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. general-purpose i/o standards such as 3.3-, 2.5-, 1.8-, and 1.5-v lvttl/lvcmos are capable of a typical 167 mhz and 1.2 lvcmos at 100 mhz interfacing frequency with 10 pf load. 1 actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations base d on your specific design and system setup to determine the maximum achievable frequency in your system. table 2?25. memory block performance specifications for cyclone v devices?preliminary (1) , (2) memory mode resources used performance unit aluts memory c6 speed grade c7, i7 speed grade c8, a7 speed grade mlab single port, all supported widths 0 1 450 380 330 mhz simple dual-port, all supported widths 0 1 450 380 330 mhz simple dual-port with read and write at the same address 0 1 350 300 250 mhz rom, all supported width 0 1 450 380 330 mhz m10k block single-port, all supported widths 0 1 315 275 240 mhz simple dual-port, all supported widths 0 1 315 275 240 mhz simple dual-port with the read-during-write option set to old data , all supported widths 0 1 275 240 180 mhz true dual port, all supported widths 0 1 315 275 240 mhz rom, all supported widths 0 1 315 275 240 mhz min pulse width (clock high time) ? ? 1,450 1,550 1,650 ps min pulse width (clock low time) ? ? 1,000 1,200 1,350 ps notes to table 2?25 : (1) to achieve the maximum memory block performance, use a memory block clock that comes thro ugh global clock routing from an on -chip pll set to 50% output duty cycle. use the quartus ii software to report ti ming for this and other memo ry block clo cking schemes. (2) when you use the error detection cyclical redundancy check (crc) featur e, there is no degradation in f max .
2?22 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet high-speed i/o specification table 2?26 lists high-speed i/o timi ng for cyclone v devices. table 2?26. high-speed i/o specifications for cyclone v devices?preliminary (2), (3) (part 1 of 2) symbol conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (4) 5 ? 437.5 5 ? 420 5 ? 320 mhz f hsclk_in (input clock frequency) single ended i/o standards clock boost factor w = 1 to 40 (4) 5 ? 320 5 ? 320 5 ? 275 mhz f hsclk_out (output clock frequency) ? 5 ? 420 5 ? 370 5 ? 320 mhz transmitter true differential i/o standards - f hsdr (data rate) serdes factor j = 4 to 10 (5) ? 840 (5) ? 740 (5) ? 640 mbps serdes factor j = 1 to 2, uses ddr registers (5) ? (7) (5) ? (7) (5) ? (7) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (6) serdes factor j = 4 to 10 (5) ? 640 (5) ? 640 (5) ? 550 mbps emulated differential i/o standards with one external output resistor network - f hsdr (data rate) (6) serdes factor j = 4 to 10 (5) ? 170 (5) ? 170 (5) ? 170 mbps t x jitter - true differential i/o standards total jitter for data rate, 600 mbps - 840 mbps ? ? 160 ? ? 160 ? ? 160 ps total jitter for data rate, < 600 mbps ? ? 0.1 ? ? 0.1 ? ? 0.1 ui t x jitter - emulated differential i/o standards with three external output resistor networks total jitter for data rate < 640 mbps ? ? tbd (1) ? ? tbd (1) ? ? tbd (1) ui t x jitter - emulated differential i/o standards with one external output resistor network total jitter for data rate < 640 mbps ? ? tbd (1) ? ? tbd (1) ? ? tbd (1) ui
chapter 2: device datasheet for cyclone v devices 2?23 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 200 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps emulated differential i/o standards with one external output resistor network ? ? 300 ? ? 300 ? ? 300 ps tccs true differential i/o standards ? ? 200 ? ? 250 ? ? 250 ps emulated differential i/o standards with three external output resistor networks ? ? 300 ? ? 300 ? ? 300 ps emulated differential i/o standards with one external output resistor network ? ? 300 ? ? 300 ? ? 300 ps receiver f hsdr (data rate) serdes factor j = 4 to 10 (5) ? 875 (6) (5) ? 840 (6) (5) ? 640 (6) mbps serdes factor j = 1 to 2, uses ddr registers (5) ? (7) (5) ? (7) (5) ? (7) mbps sampling window ? ? ? 350 ? ? 350 ? ? 350 ps notes to table 2?26 : (1) pending silicon characterization. (2) when j = 1 or 2, bypass the seri alizer/deserializer (serdes) block. (3) this is achieved by usin g the lvds clock network. (4) clock boost factor (w) is the ratio between the input data rate and the input clock rate. (5) the minimum specification depends on th e clock source (for example, the pll and cl ock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer an d input register do not have a minimum toggle rate. (6) you must calculate the leftover timing margin in the receiver by performing li nk timing closure analys is. you must consider the board skew margin, transmitter channel-to -channel skew, and receiver sampling margin to determine the leftover timing margin. (7) the maximum ideal frequen cy is the serdes factor (j) x pll max output frequency (f out ), provided you can close the design timing and the signal integrity simulation is cl ean.you can estimate the achievable maximum data rate by pe rforming link ti ming closure analys is. you must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate suppo rted. table 2?26. high-speed i/o specifications for cyclone v devices?preliminary (2), (3) (part 2 of 2) symbol conditions c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min typ max min typ max min typ max
2?24 chapter 2: device datasheet for cyclone v devices switching characteristics cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet dqs logic block and memory output clock jitter specifications table 2?27 lists the dqs phase shift error for cyclone v devices. table 2?28 lists the memory output clock jitter specifications for cyclone v devices. oct calibration block specifications table 2?29 lists the oct calibration block specifications for cyclone v devices. table 2?27. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for cyclone v devices?preliminary (1) , (2) number of dqs delay buffers c6 speed grade c7, i7 speed grade c8, a7 speed grade unit 2697080ps notes to table 2?27 : (1) the numbers are preliminary pe nding silicon ch aracterization. (2) this error specification is the absolute maximum and mi nimum error. for example, skew on two dqs delay buffers in a ?7 speed grade is 70 ps or 35 ps. (3) delay chain engineering option setting: rb_co[1:0]=?11?. table 2?28. memory output clock jitter specification for cyclone v devices?preliminary (1) , (2) , (3) parameter clock network symbol c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min max min max min max clock period jitter regional t jit(per) tbd tbd tbd tbd tbd tbd ps cycle-to-cycle period jitter regional t jit(cc) tbd tbd tbd tbd tbd tbd ps duty cycle jitter regional t jit(duty) tbd tbd tbd tbd tbd tbd ps clock period jitter global t jit(per) tbd tbd tbd tbd tbd tbd ps cycle-to-cycle period jitter global t jit(cc) tbd tbd tbd tbd tbd tbd ps duty cycle jitter global t jit(duty) tbd tbd tbd tbd tbd tbd ps notes to table 2?28 : (1) pending silicon characterization. (2) the memory output clock jitter measurements are for 200 co nsecutive clock cycles, as specified in the jedec ddr2/ddr3 sdram standard. (3) the clock jitter specification applies to the memory output clock pins generate d using differential signal-splitter and ddio circuits clocked by a pll output routed on a phy, regional, or global clock networ k as specified. altera recommends using phy clock networks whenev er possible. table 2?29. oct calibration block specifications for cyclone v devices?preliminary (part 1 of 2) symbol description min typ max unit octusrclk clock required by oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for r s oct /r t oct calibration ? 1000 ? cycles
chapter 2: device datasheet for cyclone v devices 2?25 switching characteristics february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet figure 2?1 shows the timing diagram for the oe and dyn_term_ctrl signals. duty cycle distorti on (dcd) specifications table 2?30 lists the worst-case dcd for cyclone v devices. t octshift number of octusrclk clock cycles required for oct code to shift out ? 32 ? cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between r s oct and r t oct ?2.5? ns table 2?29. oct calibration block specifications for cyclone v devices?preliminary (part 2 of 2) symbol description min typ max unit figure 2?1. timing diagram for the oe and dyn_term_ctrl signals [ table 2?30. worst-case dcd on i/o pins for cyclone v devices?preliminary symbol c6 speed grade c7, i7 speed grade c8, a7 speed grade unit min max min max min max output duty cycle 45 55 45554555 % tx rx rx oe dyn_term_ctrl t rs_rt t rs_rt tristate tristate
2?26 chapter 2: device datasheet for cyclone v devices configuration specification cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet configuration specification this section provides configuration specifications and timing for cyclone v devices. these characteristics can be designated as preliminary or final. preliminary characteristics are obtained using simulation results, process data, and other known parameters. the title of these tables show the designation as ?preliminary.? final numbers are based on actual sili con characterization and testing. the numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. there are no designations on finalized tables. por specifications table 2?31 lists the specifications for fast and standard por delay for cyclone v devices. jtag configuration timing table 2?32 lists the jtag timing parameters and values for cyclone v devices. table 2?31. fast and standard por delay specification for cyclone v devices por delay porsel pin setting minimum (ms) maximum (ms) fast (1) high 4 12 standard gnd 100 300 note to table 2?31 : (1) the maximum pulse width of the fast por delay is 12 ms, providing enough time for the pcie hard ip to initialize after the por trip. table 2?32. jtag timing parameters and values for cyclone v devices?preliminary symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (1) ns t jpzx jtag port high impedance to valid output ? 14 (1) ns t jpxz jtag port valid output to high impedance ? 14 (1) ns note to table 2?32 : (1) a 1 ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v.
chapter 2: device datasheet for cyclone v devices 2?27 configuration specification february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet fpp configuration timing this section describes the fast passive para llel (fpp) configuratio n timing parameters for cyclone v devices. dclk-to-data[] ratio (r) for fpp configuration fpp configuration requires a different dclk -to- data[] ratio when you turn on encryption or the compression feature. table 2?33 lists the dclk -to- data[] ratio for each combination. table 2?33. dclk-to-data[] ratio for cyclone v devices?preliminary (1) configuration scheme encryption compression dclk-to-data[] ratio (r) fpp (8-bit wide) off off 1 on off 1 off on 2 on on 2 fpp (16-bit wide) off off 1 on off 2 off on 4 on on 4 note to table 2?33 : (1) depending on the dclk -to- data[] ratio, the host must send a dclk frequency that is r times the data[] rate in byte per second (bps) or wo rd per second (wps). fo r example, in fpp x16 where the r is 2, the dclk frequency must be 2 times the data[] rate in wps.
2?28 chapter 2: device datasheet for cyclone v devices configuration specification cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet fpp configuration timing when dclk to data[] = 1 figure 2?2 shows the timing waveform for an fpp configuration when using a max ? ii device as an external host. this waveform shows timing when the dclk -to- data[] ratio is 1. 1 when you enable decompression or the design security feature, the dclk -to- data[] ratio varies for fpp x8 and fpp x16. for the respective dclk -to- data[] ratio, refer to table 2?33 on page 2?27 . figure 2?2. dclk-to-data[] fpp configuration timing waveform for cyclone v devices when the ratio is 1 (1) notes to figure 2?2 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic-high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the cyclone v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) for fpp x16, use data[15..0] . for fpp x8, use data[7..0] . data[15..0] are available as a user i/o pin afte r configuration. the state of this pin depends on the dual-purpose pin settings. (6) to ensure a successful configuratio n, send the entire configuratio n data to the cyclone v device. conf_done is released high when the cyclone v device receives all the configur ation data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (7) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (2) conf_done (3) dclk data[15..0] user i/o init_done word 0 word 1 word 2 word 3 t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (7) (4) user mode word n-2 word n-1 word n (6)
chapter 2: device datasheet for cyclone v devices 2?29 configuration specification february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?34 lists the timing parameters for cycl one v devices for an fpp configuration when the dclk -to- data[] ratio is 1. table 2?34. dclk-to-data[] fpp timing parameters for cyclone v devices when the ratio is 1?preliminary (1) symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (2) s t cf2st1 nconfig high to nstatus high ? 1506 (3) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency (fpp x8 and x16) ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (4) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?34 : (1) use these timing pa rameters when the dclk -to- data[] ratio is 1. to find the dclk -to- data[] ratio for your system, refer to table 2?33 on page 2?27 . (2) you can obtain this value if you do not delay configuratio n by extending the nconfig or nstatus low pulse width. (3) you can obtain this value if you do no t delay configuration by externally holding nstatus low. (4) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
2?30 chapter 2: device datasheet for cyclone v devices configuration specification cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet fpp configuration timing when dclk to data[] > 1 figure 2?3 shows the timing waveform for an fpp configuration when using a max ii device or microprocessor as an ex ternal host. this waveform shows timing when the dclk -to- data[] ratio is more than 1. figure 2?3. fpp configuration timing waveform for cyclone v devices when the dclk-to-data[] ratio is > 1 (1) , (2) notes to figure 2?3 : (1) to find the dclk -to- data[] ratio for your system, refer to table 2?33 on page 2?27 . (2) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reco nfiguration cycle begins. (3) after power up, the cyclone v device holds nstatus low for the time as specified by the por delay. (4) after power up, before and during configuration, conf_done is low. (5) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (6) ?r? denotes the dclk -to- data[] ratio. for the dclk -to- data[] ratio based on the decompression an d the design security feature enable settings, refer to table 2?33 on page 2?27 . (7) if needed, pause dclk by holding it low. when dclk restarts, the external host must provide data on the data[15..0] pins prior to sending the first dclk rising edge. (8) to ensure a successful configur ation, send the entire configurat ion data to the cyclone v device. conf_done is released high after the cyclone v device receives all th e configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (9) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (3) conf_done (4) dclk (6) data[15..0] (8) user i/o init_done t cd2um t cf2st1 t cf2cd t cfg t cf2ck t t cf2st0 t st2ck high-z user mode 12 r 12 r 12 word 0 word 1 word 3 1 t dsu t dh status t dh t ch t cl t clk word ( n -1) (7) (8) (9) (5) user mode r word n
chapter 2: device datasheet for cyclone v devices 2?31 configuration specification february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?35 lists the timing parameters for cyclone v devices when the dclk -to- data[] ratio is more than 1. table 2?35. dclk-to-data[] fpp timing parameters for cyclone v devices when the ratio is > 1?preliminary (1) symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (2) s t cf2st1 nconfig high to nstatus high ? 1506 (3) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk n?1/f dclk (4) ?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency (fpp x8 and x16) ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (5) 175 437 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?35 : (1) use these timing parameters wh en you use decompression and th e design security features. (2) this value can be obtained if you do not delay configuration by extending the nconfig or nstatus low pulse width. (3) this value can be obtained if you do no t delay configuration by externally holding nstatus low. (4) n is the dclk -to- data ratio and f dclk is the dclk frequency the system is operating. (5) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
2?32 chapter 2: device datasheet for cyclone v devices configuration specification cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet as configuration timing figure 2?4 shows the timing waveform for the acti ve serial (as) x1 mode and as x4 mode configuration timing. table 2?36 lists the timing parameters for as x1 and as x4 configurations in cyclone v devices. figure 2?4. as configuration timing for cyclone v devices notes to figure 2?4 : (1) the as scheme supports standard and fast por delay (t por ). for t por delay information, refer to ?por delay specifi cation? in the configuration, design security, and remote syst em upgrades in c yclone v devices chapter. (2) if you are using as x4 mode, this signal re presents the as_data[3..0] and epcq sends in 4-bits of data for each dclk cycle. (3) the initialization cl ock can be from the internal oscillator or the clkusr pin. (4) after the option bit to enable the init_done pin is configured into the device, init_done goes low. read address bit n - 1 bit n bit 1 bit 0 t cd2um nstatus nconfig conf_done ncso dclk as_data0/asdo as_data1 (2) init_done (4) user i/o user mode t por t dh t su t co (1) (3) table 2?36. as timing parameters for as x1 and x4 configurations in cyclone v devices?preliminary (1) , (2) symbol parameter minimum maximum unit t co dclk falling edge to the as_data0 / asdo output ? 4 s t su data setup time before the rising edge on dclk 1.5 ? ns t h data hold time after the rising edge on dclk 0?ns t cd2um conf_done high to user mode 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ?? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?36 : (1) the minimum and maximum numbers apply onl y if you choose the internal oscillator as the clock so urce for initializing the de vice. (2) the t cf2cd , t cf2st0 , t cfg , t status , and t cf2st1 timing parameters are identical to the timing parameters for p assive serial (ps) mode listed in table 2?38 on page 2?34 .
chapter 2: device datasheet for cyclone v devices 2?33 configuration specification february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet table 2?37 lists the internal clock frequency sp ecification for the as configuration scheme. ps configuration timing figure 2?5 shows the timing waveform for a ps configuration when using a max ii device or microprocessor as an external host. table 2?37. dclk frequency specification in the as configuration scheme for cyclone v devices?preliminary (1) , (2) minimum typical maximum unit 5.3 7.9 12.5 mhz 10.6 15.7 25.0 mhz 21.3 31.4 50.0 mhz 42.6 62.9 100.0 mhz notes to table 2?37 : (1) this applies to the dclk frequency specification when using the internal oscillator as the configuration clock source. (2) the as multi-device configur ation scheme does not support dclk frequency of 100 mhz. figure 2?5. ps configuration timing waveform for cyclone v devices (1) notes to figure 2?5 : (1) the beginning of this waveform shows the device in user mo de. in user mode, nconfig , nstatus , and conf_done are at logic hi gh levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) after power up, the cyclone v device holds nstatus low for the time of the por delay. (3) after power up, before and during configuration, conf_done is low. (4) do not leave dclk floating after configuration. you can drive it high or low, whichever is more convenient. (5) data0 is available as a user i/o pin after configuration. the stat e of this pin depends on the dual-purpose pin settings in the device and pins option . (6) to ensure a successful configur ation, send the entire configurat ion data to the cyclone v device. conf_done is released high after the cyclone v device receives all th e configuration data successfully. after conf_done goes high, send two additional falling edges on dclk to begin initialization and enter user mode. (7) after the option bit to enable the init_done pin is configured into the device, init_done goes low. nconfig nstatus (2) conf_done (3) dclk data0 user i/o init_done (7) bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck high-z user mode (5) (4) (6)
2?34 chapter 2: device datasheet for cyclone v devices configuration specification cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet table 2?38 lists the ps timing parameter for cyclone v devices. table 2?38. ps timing parameters for cyclone v devices?preliminary symbol parameter minimum maximum unit t cf2cd nconfig low to conf_done low ? 600 ns t cf2st0 nconfig low to nstatus low ? 600 ns t cfg nconfig low pulse width 2 ? s t status nstatus low pulse width 268 1506 (1) s t cf2st1 nconfig high to nstatus high ? 1506 (2) s t cf2ck nconfig high to first rising edge on dclk 1506 ? s t st2ck nstatus high to first rising edge of dclk 2?s t dsu data[] setup time before rising edge on dclk 5.5 ? ns t dh data[] hold time after rising edge on dclk 0?ns t ch dclk high time 0.45 x 1/f max ?ns t cl dclk low time 0.45 x 1/f max ?ns t clk dclk period 1/f max ?ns f max dclk frequency ? 125 mhz t r input rise time ? 40 ns t f input fall time ? 40 ns t cd2um conf_done high to user mode (3) 175 437 s t cd2cu conf_done high to clkusr enabled 4 x maximum dclk period ? ? t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (t init x clkusr period) ? ? t init number of clock cycles required for device initialization 17,408 ? cycles notes to table 2?38 : (1) you can obtain this value if you do not delay configuratio n by extending the nconfig or nstatus low pulse width. (2) you can obtain this value if you do no t delay configuration by externally holding nstatus low. (3) the minimum and maximum numbers apply onl y if you chose the internal oscillator as the clock sour ce for initializing the dev ice.
chapter 2: device datasheet for cyclone v devices 2?35 i/o timing february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet remote system upgrades ci rcuitry timing specification table 2?39 lists the timing parame ter specifications for the remote system upgrade circuitry. user watchdog internal osc illator frequency specification table 2?40 lists the frequency specifications for the user watchdog internal oscillator. i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the li nk timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. 1 the excel-based i/o timing spreadsheet will be available in the future release of the quartus ii software. table 2?39. remote system upgrade circuitry timing specification for cyclone v devices? preliminary parameter minimum maximum unit t max_ru_clk (1) ?40mhz t ru_nconfig (2) 250 ? ns t ru_nrstimer (3) 250 ? ns notes to table 2?39 : (1) this clock is user-supplied to the remote system upgrade circuitry. if you are using the altremote_update megafunction, the clock user-supplied to the altremote_ update megafunction must meet this specification. (2) this is equivalent to strobing the reconfiguration input of the altremote_update megafunction high for the minimum timing specification. for more information, refer to ?remote system upgrade state machine? in the device interfaces and integration basics for cyclone v devices chapter. (3) this is equivalent to st robing the reset timer input of the altr emote_update megafunction high for the minimum timing specifi cation. for more information, refer to ?user watchdog timer? in the device interfaces and integration basics fo r cyclone v devices chapter. table 2?40. user watchdog internal oscillator frequency specifications for cyclone v devices?preliminary minimum typical maximum unit 5.3 7.9 12.5 mhz
2?36 chapter 2: device datasheet for cyclone v devices i/o timing cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet programmable ioe delay table 2?41 lists the cyclone v ioe programmable delay settings. programmable output buffer delay table 2?42 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. table 2?41. ioe programmable delay for cyclone v devices (1) parameter available settings minimum offset fast model slow model unit industrial commercial c6 speed grade c7, i7 speed grade c8, a7 speed grade tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns tbd tbd tbd tbd tbd tbd tbd tbd ns note to table 2?41 : (1) pending data extraction from the quartus ii software. table 2?42. programmable output buffer delay for cyclone v devices?preliminary (1) , (2) symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps notes to table 2?42 : (1) pending data extraction fr om the quartus ii software. (2) you can set the progra mmable output buffer de lay in the quartus ii software by setting the output buffer delay control assignment to either positive, negati ve, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment.
chapter 2: device datasheet for cyclone v devices 2?37 glossary february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet glossary table 2?43 lists the glossary for this chapter. table 2?43. glossary table (part 1 of 4) letter subject definitions a b c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block?maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block?maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g h i ?? single-ended waveform differential waveform positi v e channel (p) = v ih n egati v e channel (n) = v il gro u nd v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positi v e channel (p) = v oh n egati v e channel (n) = v ol gro u nd v od v od v od p ? n = 0 v v cm
2?38 chapter 2: device datasheet for cyclone v devices glossary cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet j j high-speed i/o block?deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k l m n o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? r r l receiver differential input discrete resistor (external to the cyclone v device). table 2?43. glossary table (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n pfd switchover delta sigma modulator vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c17 4
chapter 2: device datasheet for cyclone v devices 2?39 glossary february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet s sampling window (sw) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for the sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: single-ended voltage referenced i/o standard t t c high-speed receiver/transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including the t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block?duty cycle on high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and the data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input t outpj_io period jitter on the general purpose i/o driven by a pll t outpj_dc period jitter on the dedicated clock output driven by a pll t rise signal low-to-high transition time (20?80%) u ?? table 2?43. glossary table (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling w indo w (s w ) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
2?40 chapter 2: device datasheet for cyclone v devices document revision history cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet document revision history table 2?44 lists the revision history for this chapter. v v cm(dc) dc common mode input voltage. v icm input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage v ih(dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage v il(dc) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block?clock boost factor x y z ?? table 2?43. glossary table (part 4 of 4) letter subject definitions table 2?44. document revision history date version changes february 2012 1.2 added automotive speed grade information. added figure 2?1 . updated table 2?3 , table 2?8 , table 2?9 , table 2?20 , table 2?21 , table 2?22 , table 2?23 , table 2?24 , table 2?25 , table 2?26 , table 2?27 , table 2?28 , table 2?30 , table 2?35 , and table 2?41 . minor text edits. november 2011 1.1 added table 2?5. updated table 2?3, table 2?4, table 2?11, table 2?13, table 2?20, and table 2?21. october 2011 1.0 initial release.
chapter 2: device datasheet for cyclone v devices 2?41 document revision history february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet
2?42 chapter 2: device datasheet for cyclone v devices document revision history cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet
february 2012 altera corporation cyclone v device handbook volume 1: device overview and datasheet additional information this chapter provides additional info rmation about the document and altera. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature nontechnical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicate keyboard keys and menu names. for example, the delete key and the options menu. ?subheading title? quotation marks indicate references to sections in a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information typographic conventions cyclone v device handbook february 2012 altera corporation volume 1: device overview and datasheet courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h the question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. m the multimedia icon directs you to a related multimedia presentation. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning

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